Summary of EEE348 PENGANTAR REKABENTUK LITAR BERSEPADU (INTRODUCTION TO INTEGRATED CIRCUIT DESIGN)

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EEE348 PENGANTAR REKABENTUK LITAR BERSEPADU (INTRODUCTION TO INTEGRATED CIRCUIT DESIGN)

MEMPELAJARI METODOLOGI UNTUK MENGANALISIS DAN MEREKA BENTUK LITAR BERSEPADU DIGITAL.

Lecturer: DR. JAGADHESWARAN A/L RAJENDRAN
Lecturer: PROFESOR MADYA DR. BAKHTIAR AFFENDI BIN ROSDI

Skill Level: Beginner

General

Announcements

25 March - 31 March

EEE 348 Overview

Chapter 1 Introduction

Chapter 2 Design Methodology

EEE348 Whats app Group

Cadence Lab Manual 1 (IC5)

Cadence Lab Manual (IC6)

Cadence Server username and server number

1 April - 7 April

Chapter 3 Layout Verification

Chapter 4 MOS Transistors

Mini Project 2023/24

8 April - 14 April

Chapter 5 CMOS Fabrication

15 April - 21 April

Chapter 6 Logic to Layout

22 April - 28 April

Chapter 7 Memory

Assignment 1 Dr Jaga

Assignment 1 Dr Jaga

20 May - 26 May

01 LectureNotes 23May2024

ModelSim RelatedFiles

Submission of proof execution of Verilog Simulator (ModelSim or others)

02 Lecture notes for 24 May 2024

Exercise 1

Submission of Exercise 1

27 May - 2 June

03 LectureNotes 30May2024

Exercise 2

Submission of Exercise 2

04 LectureNotes 31May2024

Exercise 3

Submission of Exercise 3

3 June - 9 June

No class on 6th June 2024

For class on 7th June (Please see following youtube video)

Digital IC EDA

Revised Tentative Schedule

10 June - 16 June

FSM Verilog

FSM Frequency Divider

MiniProject2

14 June 2024 (Lab 1:VCS at MicroComputer Lab)

Lab1 VCS

Submit simulation waveform by VCS

17 June - 23 June

Lab2 DC

Lab3 FPGA

videos

24 June - 30 June

FSM Assignment Verilog

Submission of Assignment

28 June 2024 (9.00 am - 10.00 am) :Test 2 at DK10

1 July - 7 July

Submission of Mini Project (One per group)

Please login using USM Identity